Many high performance circuits such as for example, microprocessors, use dynamic logic gates. Dynamic gates generally have shorter delays than conventional static logic gates, which allow the high performance circuit to be faster. Typically, dynamic gates have a precharge phase and an evaluation phase. To ensure correct operation, typical dynamic logic gates require that the input signal received by a dynamic gate must either: (a) be stable before the beginning of the evaluation phase; or (b) transition in only one predetermined direction during the evaluation phase. For example, the dynamic logic gate may require that during the precharge phase, the input signal be at a low voltage level and, thus, only low-to high transitions are allowed during the evaluation phase.
In operation, dynamic logic gates generally cause their output signal(s) to conform to their input signal requirements. For example, a dynamic logic gate that allows low-to-high transitions during evaluation phases generally would cause its output signal(s) to be at logic low level during the precharge phase. Then, during the evaluation phase, the dynamic logic gate would cause the output signal(s) to either remain at a logic low level or transition to a logic high level, depending on the dynamic logic gate's logic operation on the input signal(s) received during the evaluation phase.
A problem arises when static flip-flops are used to drive dynamic logic gates. Conventional static flip-flops generally have uncertainty in when tile flip-flops' output signals become stable. Consequently, depending on the clock rate, the time required for a conventional static flip-flop's output signals to become stable may extend into the evaluation phase of the dynamic logic gate that the static flip-flop is driving. Further, a conventional static flip-flop can, of course, provide outputs that transition in both directions (i.e., from high-to-low output voltage and low-to-high output voltage). These properties of static flip-flops can violate the requirements for driving dynamic logic gates.
One conventional solution is to operate the static flip-flop and dynamic logic gates at a slower clock rate, giving the static flip-flop adequate time to provide stable output signals to the dynamic logic gate before the dynamic logic gate enters the evaluation period. Of course, high clock speeds are desirable in most applications. Thus, this solution may not be practical for many applications. Another conventional solution is to delay the evaluation phase of the dynamic flip-flop until the static flip-flop output signals are stable, as described below in conjunction with FIG. 1.
FIG. 1 is a block diagram illustrating a circuit 100 using a conventional evaluation delay scheme. A static flip-flop 101 has an output lead 103 connected to an input lead 105 of a dynamic logic gate 107. The dynamic logic gate 107 has an output lead 108 connected to an input lead 109 of another dynamic logic gate 111. A clock signal CK is provided to a clock input terminal of tile static flip-flop 101 through a clock line 115. A delay circuit 117 has an input lead 119 connected to the clock line 115, and provides at an output lead 121 a clock signal CKD, which is a delayed version of the clock signal CK. The output lead 121 of the delay circuit 117 is connected to clock input terminals of the dynamic logic gates 107 and 111. In this example, the dynamic logic gates 107 and 111 operate correctly only with stable data input signals or low-to-high transitions during the evaluation phase, and their output signals will be either stable data or low-to-high transitions during this phase.
In the conventional circuit 100, the dynamic logic gates 107 and 111 enter the evaluation phase when the clock signal CKD is high (i.e., during the logic high portion of the clock cycle) and in the precharge phase when the received clock signal is low (i.e., during the logic low portion of the clock cycle). Thus, the delay circuit 117 delays the evaluation phase of the dynamic logic gates 107 and 111 relative to the clock signal CK for a time period .DELTA.. The duration of tile time period .DELTA. is predetermined to ensure that the dynamic logic gate 107 receives a fully stable data signal (i.e., the output signal X from the static flip-flop 101) before the start of the evaluation phase and to account for clock skew and jitter between the signals CK and CKD. Of course, this delay imposes a constraint that limits the frequency of the clock signal CK, which is undesirable in most applications.
FIG. 2 is a timing diagram illustrative of the operation of the circuit 100 (FIG. 1). The waveform 201 represents the clock signal CK, which is received by the static flip-flop 101 (FIG. 1). The delay circuit 117 also receives the clock signal CK, which it delays by the time period .DELTA. to generate the signal CKD, represented by the waveform 203. The delay circuit 117 introduces skew and jitter, as indicated by multiple-rising edges 204 of the waveform 203. For timing purposes, the maximum skew (i.e., the last rising edge 205 of the edges 204) is used in determining the speed of the circuit.
On the rising edge of the clock signal CK, the flip-flop 101 loads in a logic value received at its input terminal, and then generates an output signal X after a short propagation delay, represented by the waveform 207. Because the flip-flop 101 is a static flip-flop, the output signal X may transition from either high-to-low or low-to-high, as shown by the waveform 207.
The output signal X is received at the data input terminal of the dynamic logic gate 107 (FIG. 1). At the end of the time period .DELTA. (measured from the rising edge of the clock signal CK), the output signal X is fully stable and the rising edge of the delayed clock signal CKD causes the dynamic logic gates 107 and 111 (FIG. 1) to enter the evaluation phase. As a result, the dynamic logic gate 107 operates on the signal X to generate an output signal Y, which is represented by the waveform 209. The output signal Y is received by the dynamic logic gate 111. In this example, the output signal Y makes a low-to-high transition during the evaluation phase, after a propagation delay incurred by the dynamic logic gate 107.
Ideally, the dynamic gate 107 would start operating on its input signal immediately upon the end of the propagation delay from the flip-flop 101. As shown in FIG. 2, the circuit 100 (FIG. 1) does not achieve this goal. The time period between the rising edge 205 and the end of the propagation delay of the static flip-flop 101 is the time penalty incurred by using the static flip-flop 101. Thus, there is a need for a flip-flop for use with dynamic logic gates that eliminates this time penalty.